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https://github.com/signalwire/freeswitch.git
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d2edcad66e
Thanks to Phil Zimmermann for the code and for the license exception we needed to include it. There remains some build system integration work to be done before this code will build properly in the FreeSWITCH tree.
80 lines
2.9 KiB
C
80 lines
2.9 KiB
C
/*
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* lbnarm.h - This file defines the interfaces to the ARM
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* assembly primitives. It is intended to be included in "lbn.h"
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* via the "#include BNINCLUDE" mechanism.
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*/
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#define BN_LITTLE_ENDIAN 1
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typedef unsigned bnword32;
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#define BNWORD32 bnword32
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/* Function prototypes for the asm routines */
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void
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lbnMulN1_32(bnword32 *out, bnword32 const *in, unsigned len, bnword32 k);
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#define lbnMulN1_32 lbnMulN1_32
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bnword32
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lbnMulAdd1_32(bnword32 *out, bnword32 const *in, unsigned len, bnword32 k);
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#define lbnMulAdd1_32 lbnMulAdd1_32
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/* Not implemented yet */
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bnword32
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lbnMulSub1_32(bnword32 *out, bnword32 const *in, unsigned len, bnword32 k);
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#define lbnMulSub1_32 lbnMulSub1_32
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#if __GNUC__ && 0
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/*
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* Use the (massively cool) GNU inline-assembler extension to define
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* inline expansions for various operations.
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*
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* The massively cool part is that the assembler can have inputs
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* and outputs, and you specify the operands and which effective
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* addresses are legal and they get substituted into the code.
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* (For example, some of the code requires a zero. Rather than
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* specify an immediate constant, the expansion specifies an operand
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* of zero which can be in various places. This lets GCC use an
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* immediate zero, or a register which contains zero if it's available.)
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*
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* The syntax is asm("asm_code" : outputs : inputs : trashed)
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* %0, %1 and so on in the asm code are substituted by the operands
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* in left-to-right order (outputs, then inputs).
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* The operands contain constraint strings and values to use.
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* Outputs must be lvalues, inputs may be rvalues. In the constraints:
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* "r" means that the operand may be in a register.
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* "=" means that the operand is assigned to.
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* "%" means that this operand and the following one may be
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* interchanged if desirable.
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* "&" means that this output operand is written before the input operands
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* are read, so it may NOT overlap with any input operands.
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* "0" and "1" mean that this operand may be in the same place as the
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* given operand.
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* Multiple sets of constraints may be listed, separated by commas.
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*
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* Note that ARM multi-precision multiply syntax lists destLo before destHi.
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* Also, the first source (%2) may not be the same as %0 or %1.
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* The second source, however, may be.
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*/
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/* (ph<<32) + pl = x*y */
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#define mul32_ppmm(ph,pl,x,y) \
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__asm__("umull %1,%0,%2,%3" : "=&r,&r"(ph), "=&r,&r"(pl) \
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: "%r,%r"(x), "r0,r1"(y))
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/* (ph<<32) + pl = x*y + a */
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#define mul32_ppmma(ph,pl,x,y,a) \
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__asm__("umlal %1,%0,%2,%3" : "=&r"(ph), "=&r"(pl) \
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: "%r"(x), "r"(y), "0"(0), "1"(a))
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/* (ph<<32) + pl = x*y + a + b */
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/* %4 (a) may share a register with %0, but nothing else may. */
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#define mul32_ppmmaa(ph,pl,x,y,a,b) \
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__asm__("adds %1, %4, %5\n\t" \
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"movcc %0, #0\n\t" \
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"movcs %0, #1\n\t" \
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"umlal %1,%0,%2,%3" \
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: "=&r"(ph), "=&r"(pl) \
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: "%r"(x), "r"(y), "%r"(a), "r1"(b))
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#endif /* __GNUC__ */
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