mirror of
https://github.com/signalwire/freeswitch.git
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d2edcad66e
Thanks to Phil Zimmermann for the code and for the license exception we needed to include it. There remains some build system integration work to be done before this code will build properly in the FreeSWITCH tree.
174 lines
4.9 KiB
ArmAsm
174 lines
4.9 KiB
ArmAsm
@ lbnarm.s - 32-bit bignum primitives for ARM processors with 32x32-bit multiply
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@
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@ This uses the standard ARM calling convetion, which is that arguments
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@ are passed, and results returned, in r0..r3. r0..r3, r12 (IP) and r14 (LR)
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@ are volatile across the function; all others are callee-save.
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@ However, note that r14 (LR) is the return address, so it would be
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@ wise to save it somewhere before trashing it. Fortunately, there is
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@ a neat trick possible, in that you can pop LR from the stack straight
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@ into r15 (PC), effecting a return at the same time.
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@
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@ Also, r13 (SP) is probably best left alone, and r15 (PC) is obviously
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@ reserved by hardware. Temps should use lr, then r4..r9 in order.
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.text
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.align 2
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@ out[0..len] = in[0..len-1] * k
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@ void lbnMulN1_32(BNWORD32 *out, BNWORD32 const *in, unsigned len, BNWORD32 k)
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.global lbnMulN1_32
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.type lbnMulN1_32, %function
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lbnMulN1_32:
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stmfd sp!, {r4, r5, lr}
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ldr lr, [r1], #4 @ lr = *in++
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umull r5, r4, lr, r3 @ (r4,r5) = lr * r3
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str r5, [r0], #4 @ *out++ = r5
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movs r2, r2, lsr #1
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bcc m32_even
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mov r5, r4 @ Get carry in the right register
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beq m32_done
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m32_loop:
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@ carry is in r5
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ldr lr, [r1], #4 @ lr = *in++
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mov r4, #0
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umlal r5, r4, lr, r3 @ (r4,r5) += lr * r3
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str r5, [r0], #4 @ *out++ = r5
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m32_even:
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@ carry is in r4
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ldr lr, [r1], #4 @ lr = *in++
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mov r5, #0
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umlal r4, r5, lr, r3 @ (r5,r4) += lr * r3
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subs r2, r2, #1
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str r4, [r0], #4 @ *out++ = r4
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bne m32_loop
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m32_done:
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str r5, [r0, #0] @ store carry
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ldmfd sp!, {r4, r5, pc}
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.size lbnMulN1_32, .-lbnMulN1_32
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@ out[0..len-1] += in[0..len-1] * k, return carry
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@ BNWORD32
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@ lbnMulAdd1_32(BNWORD32 *out, BNWORD32 const *in, unsigned len, BNWORD32 k)
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.global lbnMulAdd1_32
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.type lbnMulAdd1_32, %function
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lbnMulAdd1_32:
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stmfd sp!, {r4, r5, lr}
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mov r4, #0
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ldr lr, [r1], #4 @ lr = *in++
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ldr r5, [r0, #0] @ r5 = *out
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mov r4, #0
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umlal r5, r4, lr, r3 @ (r4,r5) += lr * r3
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str r5, [r0], #4 @ *out++ = r5
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movs r2, r2, lsr #1
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bcc ma32_even
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beq ma32_done
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ma32_loop:
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@ carry is in r4
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ldr lr, [r1], #4 @ lr = *in++
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mov r5, #0
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umlal r4, r5, lr, r3 @ (r5,r4) += lr * r3
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ldr lr, [r0, #0] @ lr = *out
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adds lr, lr, r4 @ lr += product.low
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str lr, [r0], #4 @ *out++ = lr
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adc r4, r5, #0 @ Compute carry and move back to r4
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ma32_even:
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@ another unrolled copy
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ldr lr, [r1], #4 @ lr = *in++
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mov r5, #0
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umlal r4, r5, lr, r3 @ (r5,r4) += lr * r3
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ldr lr, [r0, #0] @ lr = *out
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adds lr, lr, r4 @ lr += product.low
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adc r4, r5, #0 @ Compute carry and move back to r4
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str lr, [r0], #4 @ *out++ = lr
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subs r2, r2, #1
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bne ma32_loop
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ma32_done:
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mov r0, r4
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ldmfd sp!, {r4, r5, pc}
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.size lbnMulAdd1_32, .-lbnMulAdd1_32
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@@@ This is a bit messy... punt for now...
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@ out[0..len-1] -= in[0..len-1] * k, return carry (borrow)
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@ BNWORD32
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@ lbnMulSub1_32(BNWORD32 *out, BNWORD32 const *in, unsigned len, BNWORD32 k)
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.global lbnMulSub1_32
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.type lbnMulSub1_32, %function
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lbnMulSub1_32:
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stmfd sp!, {r4, r5, lr}
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mov r4, #0
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mov r5, #0
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ldr lr, [r1], #4 @ lr = *in++
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umull r4, r5, lr, r3 @ (r5,r4) = lr * r3
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ldr lr, [r0, #0] @ lr = *out
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subs lr, lr, r4 @ lr -= product.low
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str lr, [r0], #4 @ *out++ = lr
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addcc r5, r5, #1 @ propagate carry
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movs r2, r2, lsr #1
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bcc ms32_even
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mov r4, r5
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beq ms32_done
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ms32_loop:
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@ carry is in r4
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ldr lr, [r1], #4 @ lr = *in++
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mov r5, #0
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umlal r4, r5, lr, r3 @ (r5,r4) += lr * r3
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ldr lr, [r0, #0] @ lr = *out
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subs lr, lr, r4 @ lr -= product.low
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str lr, [r0], #4 @ *out++ = lr
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addcc r5, r5, #1 @ propagate carry
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ms32_even:
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@ carry is in r5
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ldr lr, [r1], #4 @ lr = *in++
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mov r4, #0
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umlal r5, r4, lr, r3 @ (r4,r5) += lr * r3
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ldr lr, [r0, #0] @ lr = *out
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subs lr, lr, r5 @ lr -= product.low
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str lr, [r0], #4 @ *out++ = lr
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addcc r4, r4, #1 @ Propagate carry
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subs r2, r2, #1
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bne ms32_loop
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ms32_done:
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mov r0, r4
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ldmfd sp!, {r4, r5, pc}
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.size lbnMulSub1_32, .-lbnMulSub1_32
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@@
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@@ It's possible to eliminate the store traffic by doing the multiplies
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@@ in a different order, forming all the partial products in one column
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@@ at a time. But it requires 32x32 + 64 -> 65-bit MAC. The
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@@ ARM has the MAC, but no carry out.
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@@
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@@ The question is, is it faster to do the add directly (3 instructions),
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@@ or can we compute the carry out in 1 instruction (+1 to do the add)?
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@@ Well... it takes at least 1 instruction to copy the original accumulator,
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@@ out of the way, and 1 to do a compare, so no.
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@@
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@@ Now, the overall loop... this is an nxn->2n multiply. For i=0..n-1,
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@@ we sum i+1 multiplies in each (plus the carry in from the
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@@ previous one). For i = n..2*n-1 we sum 2*n-1-i, plus the previous
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@@ carry.
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@@
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@@ This "non-square" structure makes things more complicated.
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@@
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@@ void
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@@ lbnMulX_32(BNWORD32 *prod, BNWORD32 const *num1, BNWORD32 const *num2,
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@@ unsigned len)
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@ .global lbnMulX_32
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@ .type lbnMulX_32, %function
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@lbnMulX_32:
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@ stmfd sp!, {r4, r5, r6, r7, lr}
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@
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@ mov r4, #0
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@ mov r5, #0
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@ mov r0, r4
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@ ldmfd sp!, {r4, r5, pc}
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@ .size lbnMulX_32, .-lbnMulX_32
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